1. Field of the Invention
The invention relates to a method of fabricating a dynamic random access memory (DRAM), and more particularly to a method of fabricating a self-aligned node contact window.
2. Description of the Related Art
As semiconductor device integration increases, device dimensions need to reduce in accordance with the design rule. The line width of the node contact is also reduced as the dimensions of a DRAM capacitor decrease. Therefore, using conventional photolithography to pattern the node contact becomes more and more difficult. If the pattern of the node contact window is misaligned, the position of the node contact window shifts. The quality of the device becomes worse and shorts easily occur in the device.
FIG. 1 is a cross-sectional view of a node contact. A DRAM is formed on an active region defined by the isolation region 101 on the surface of the substrate 100. The field effect transistor (FET) 102 includes a gate structure 103 and a source/drain region 104, 105. The gate structure 103 also includes a cap layer 109 formed thereon and a spacer 110 formed on the sidewall. An insulating layer 112 is formed over the substrate 100 and a self-aligned contact 114 is next formed by patterning the insulating layer. A conductive layer is deposited and defined to form a bit line 122 of the DRAM, such that the bit line 122 is electrically coupled with the source/drain region 104 of the transistor 102.
A layer of silicon oxide 126 is deposited over the substrate 100 and a layer of BPSG 128 is then formed and planarized on the silicon oxide layer 126. These layers of BPSG 128 and silicon oxide 126 are patterned to form a node contact window 134. A capacitor is next formed but it is not necessary to describe here the detailed process of the formation of the capacitor since it doesn't belong to the field of the invention.
However, as line width is reduced, it becomes more difficult to form the node contact window 134 of the capacitor by patterning the BPSG 128 and silicon oxide 126 using photolithography. If a misalignment occurs in the pattern of the node contact window, its position shifts and the bit line 122 is damaged by etching, thus short occurs between the conductive material subsequently deposited in the node contact window and the bit line 122.